Thu 20 Jul 2023 10:30 - 10:45 at Smith Classroom (Gates G10) - ISSTA 10: Test Optimizations Chair(s): Wing Lam

Regression test selection (RTS) speeds up regression testing by only re-running tests that might be affected by code changes. Ideal RTS safely selects all affected tests and precisely selects only affected tests. But, aiming for this ideal is often slower than re-running all tests. So, recent RTS techniques use program analysis to trade precision for speed, i.e., lower regression testing time, or even use machine learning to trade safety for speed. We seek to make recent analysis-based RTS techniques more precise, to further speed up regression testing. Independent studies suggest that these techniques reached a “performance wall” in the speed-ups that they provide.
We manually inspect code changes to discover those that do not require re-running tests that are only affected by such changes. We categorize 29 kinds of changes that we find from five projects into 13 findings, 11 of which are semantics-modifying. We enhance two RTS techniques—Ekstazi and STARTS—to reason about our findings. Using 1,150 versions of 23 projects, we evaluate the impact on safety and precision of leveraging such changes. We also evaluate if our findings from a few projects can speed up regression testing in other projects. The results show that our enhancements are effective and they can generalize. On average, they result in selecting 41.7% and 31.8% fewer tests, and take 33.7% and 28.7% less time than Ekstazi and STARTS, respectively, with no loss in safety.

Thu 20 Jul

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10:30 - 12:00
ISSTA 10: Test OptimizationsTechnical Papers at Smith Classroom (Gates G10)
Chair(s): Wing Lam University of Illinois at Urbana-Champaign
10:30
15m
Talk
More Precise Regression Test Selection via Reasoning about Semantics-Modifying ChangesACM SIGSOFT Distinguished Paper
Technical Papers
Yu Liu University of Texas at Austin, Jiyang Zhang University of Texas at Austin, Pengyu Nie University of Texas at Austin, Milos Gligoric University of Texas at Austin, Owolabi Legunsen Cornell University
DOI
10:45
15m
Talk
Catamaran: Low-Overhead Memory Safety Enforcement via Parallel Acceleration
Technical Papers
Yiyu Zhang Nanjing University, Tianyi Liu Nanjing University, Zewen Sun Nanjing University, Zhe Chen Nanjing University of Aeronautics and Astronautics, Xuandong Li Nanjing University, Zhiqiang Zuo Nanjing University
DOI
11:00
15m
Talk
Applying and Extending the Delta Debugging Algorithm for Elevator Dispatching Algorithms (Experience Paper)
Technical Papers
Pablo Valle Mondragon University, Aitor Arrieta Mondragon University, Maite Arratibel Orona
DOI Pre-print
11:15
15m
Talk
June: A Type Testability Transformation for Improved ATG Performance
Technical Papers
Dan Bruce University College London, David Kelly King’s College London, Hector Menendez King’s College London, Earl T. Barr University College London; Google DeepMind, David Clark University College London
DOI
11:30
15m
Talk
Pattern-Based Peephole Optimizations with Java JIT Tests
Technical Papers
Zhiqiang Zang University of Texas at Austin, Aditya Thimmaiah University of Texas at Austin, Milos Gligoric University of Texas at Austin
DOI Pre-print
11:45
15m
Talk
GPUHarbor: Testing GPU Memory Consistency at Large (Experience Paper)ACM SIGSOFT Distinguished Artifact
Technical Papers
Reese Levine University of California at Santa Cruz, Mingun Cho University of California at Davis, Devon McKee University of California at Santa Cruz, Andrew Quinn University of California at Santa Cruz, Tyler Sorensen University of California at Santa Cruz
DOI